`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2024/11/13 16:20:51
// Design Name: 
// Module Name: adc2IaIbIc
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments: I = (( (Vs_adc - Vref_adc) * 3.3 * 9200 ) / ( 4096 * 3240) ) ^ 16
//                        = ( (Vs_adc - Vref_adc) * 9.37037)^5
//                        9.37 = ( 8 + 2  - 0.5 - 0.125)
//////////////////////////////////////////////////////////////////////////////////



module adc2IaIbIc(
    input                   sys_clk_i                       ,
    input                   sys_rst_n_i                     , 

    input                   adc2IaIbIc_req_i                ,
    output                  adc2IaIbIc_ack_o                ,

    input[15:0]             adc_channel_u_i                 ,
    input[15:0]             adc_channel_v_i                 ,
    input[15:0]             adc_channel_w_i                 ,

    input[15:0]             adc_channel_u_offset_i          ,
    input[15:0]             adc_channel_v_offset_i          ,
    input[15:0]             adc_channel_w_offset_i          ,
    

    output reg signed[31:0] Ia_o                            ,
    output reg signed[31:0] Ib_o                            ,
    output reg signed[31:0] Ic_o                            
);


reg[3:0]            delay;
reg signed[15:0]    voltage_channel_u_value;
reg signed[15:0]    voltage_channel_v_value;
reg signed[15:0]    voltage_channel_w_value;

reg signed[15:0]    voltage_channel_u_value_t;
reg signed[15:0]    voltage_channel_v_value_t;
reg signed[15:0]    voltage_channel_w_value_t;


assign adc2IaIbIc_ack_o = ( delay == 4'b1000) ? 1'b1 : 1'b0;

always@( posedge sys_clk_i or negedge sys_rst_n_i ) begin
    if( sys_rst_n_i == 1'b0 )
        delay <= 4'd0;
    else if( adc2IaIbIc_req_i == 1'b1 && delay == 6'd0)
        delay <= {3'd0 , adc2IaIbIc_req_i};
    else
        delay <= {delay[2:0],1'b0};
end



always@( posedge sys_clk_i or negedge sys_rst_n_i ) begin
    if( sys_rst_n_i == 1'b0 ) begin
        voltage_channel_u_value_t <= 'd0;
        voltage_channel_v_value_t <= 'd0;
        voltage_channel_w_value_t <= 'd0;
    end
    else if( delay == 4'b0001 ) begin
        voltage_channel_u_value_t <= ( voltage_channel_u_value >>> 1 ) + ( voltage_channel_u_value >>> 3 );
        voltage_channel_v_value_t <= ( voltage_channel_v_value >>> 1 ) + ( voltage_channel_v_value >>> 3 );
        voltage_channel_w_value_t <= ( voltage_channel_w_value >>> 1 ) + ( voltage_channel_w_value >>> 3 );
    end
    else;
end

always@( posedge sys_clk_i or negedge sys_rst_n_i ) begin
    if( sys_rst_n_i == 1'b0 ) begin
        voltage_channel_u_value <= 'd0;
        voltage_channel_v_value <= 'd0;
        voltage_channel_w_value <= 'd0;
    end
    else if( adc2IaIbIc_req_i == 1'b1 ) begin
        voltage_channel_u_value <= $signed(adc_channel_u_i) - $signed(adc_channel_u_offset_i);
        voltage_channel_v_value <= $signed(adc_channel_v_i) - $signed(adc_channel_v_offset_i);
        voltage_channel_w_value <= $signed(adc_channel_w_i) - $signed(adc_channel_w_offset_i);
    end
    else if( delay == 4'b0001 ) begin
        voltage_channel_u_value <=  ( voltage_channel_u_value <<< 3 ) + ( voltage_channel_u_value <<< 1);
        voltage_channel_v_value <=  ( voltage_channel_v_value <<< 3 ) + ( voltage_channel_v_value <<< 1);
        voltage_channel_w_value <=  ( voltage_channel_w_value <<< 3 ) + ( voltage_channel_w_value <<< 1);
    end
    else if( delay == 4'b0010 ) begin
        voltage_channel_u_value <= voltage_channel_u_value - voltage_channel_u_value_t;
        voltage_channel_v_value <= voltage_channel_v_value - voltage_channel_v_value_t;
        voltage_channel_w_value <= voltage_channel_w_value - voltage_channel_w_value_t;

    end
    else begin
        voltage_channel_u_value <= voltage_channel_u_value;
        voltage_channel_v_value <= voltage_channel_v_value;
        voltage_channel_w_value <= voltage_channel_w_value;
    end
end


always@( posedge sys_clk_i or negedge sys_rst_n_i ) begin
    if( sys_rst_n_i == 1'b0 ) begin
        Ia_o <= 'd0;
        Ib_o <= 'd0;
        Ic_o <= 'd0;
    end
    else if( delay == 4'b0100 ) begin
        Ia_o <= voltage_channel_u_value <<< 5;
        Ib_o <= voltage_channel_v_value <<< 5;
        Ic_o <= voltage_channel_w_value <<< 5;
    end
    else;
end



endmodule
